1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More specifically, the present invention relates to a level shifter circuit that can switch voltage levels expeditiously.
2. Description of the Related Art
A semiconductor integrated circuit typically contains a large number of circuit units with different functions. These circuit units may operate on various voltage levels. To interface circuit units operating on different voltage levels, a level shifter circuit is used to receive an input signal of a first voltage level V1 and to produce an output signal of a second voltage level V2. FIGS. 1A and 1B illustrate two types of traditional level shifter circuits. Both types primarily comprise two PMOS transistors and two NMOS transistors but connect differently.
FIG. 1A shows the first type of a traditional level shifter circuit which comprises a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The first PMOS transistor P1 is connected in series with the first NMOS transistor N1. The second PMOS transistor P2 is connected in series with the second NMOS transistor N2. The gate of the first PMOS transistor P1 is connected to the node B, the common node of the second PMOS transistor P2 and the second NMOS transistor N2. The gate of the second PMOS transistor P2 is connected to the node A, the common node of the first PMOS transistor P1 and the first NMOS transistor N1. The gate of the first NMOS transistor N1 is connected to a voltage, which is at the lower voltage level of V1 and V2, to turn on the first NMOS transistor N1. The source of the second NMOS transistor N2 is connected to a third voltage Vss, for example, the ground. An input signal of a first voltage level V1 (logic high) or third voltage level Vss (logic low) is provided to the drain of the first NMOS transistor N1 and the gate of the second NMOS transistor N2. The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply terminal of the second voltage level V2. An output signal of the second voltage level V2 (logic high) or the third voltage level Vss (logic low) is generated from the node B. The output signal is in the inversed state of the input signal. When the input signal is at logic high of the first voltage level V1, the output signal is at logic low of the third voltage level Vss, for example, the zero voltage. When the input signal is at logic low of the third voltage level Vss, for example, the zero voltage, the output signal is at logic high of the second voltage level V2.
Originally, the input signal is at logic high of the first voltage level V1 and the output signal is at logic low of the third voltage level Vss. When the input signal is switched to the logic low of the third voltage level Vss, the node A receives the third voltage Vss because the first NMOS transistor N1 is turned on. The third voltage Vss is also transmitted to the gate of the second NMOS transistor N2 to turn it off. However, the second PMOS transistor P2, upon its gate receiving the third voltage Vss, is turned on to gradually pull up the voltage of the node B to the second voltage level V2. After the voltage of node B is pulled up, the first PMOS transistor P1 is turned off and the voltage of the node A remains at the third voltage Vss. The output signal from the node B reaches the voltage level V2 with a time delay after the input signal is switched from the logic high to the logic low.
Similarly, when the input signal is switched from the logic low back to the logic high of the first voltage level V1, the node A receives the first voltage V1 because the first NMOS transistor N1 is turned on. The first voltage V1 is also transmitted to the gate of the second NMOS transistor N2 to turn it on. The voltage of the node B is gradually pulled down from the second voltage V2 to the third voltage Vss. After the voltage of the node B is pulled down, the first PMOS transistor P1 is turned on and the voltage of node A becomes at the second voltage V2. The output signal from the node B reaches the third voltage level Vss with a time delay after the input signal is switched from the logic low to the logic high.
In addition, at the moment the second NMOS transistor N2 is turned on by the input signal of the first voltage level V1, the second PMOS transistor P2 has not been completely turned off. As a result, a leakage current flows from the power supply terminal of the second voltage level V2 to the third voltage Vss terminal, for example, the ground.
FIG. 1B shows the second type of a traditional level shifter circuit which comprises a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and an inverter I1. The first PMOS transistor P1 is connected in series with the first NMOS transistor N1. The second PMOS transistor P2 is connected in series with the second NMOS transistor N2. The gate of the first PMOS transistor P1 is connected to the node B, the common node of the second PMOS transistor P2 and the second NMOS transistor N2. The gate of the second PMOS transistor P2 is connected to the node A, the common node of the first PMOS transistor P1 and the first NMOS transistor N1. The sources of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to a third voltage level Vss, for example, the ground. An input signal of the first voltage level V1 is provided to the gate of the second NMOS transistor N2. The input signal of the first voltage level V1 is inversed through the inverter I1 and the inversed input signal is provided to the gate of the first NMOS transistor N1. The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply of the second voltage level V2. An output signal of the second voltage level V2 is generated from the node B. The output signal is in the inversed state of the input signal. When the input signal is at logic high of the first voltage level V1, the output signal is at logic low of the third voltage level Vss. When the input signal is at logic low of the third voltage level Vss, the output signal is at logic high of the second voltage level V2. The second type of the traditional level shifter circuit operates in a similar manner to the first type of the traditional level shifter circuit. Thus, it also causes problems of time delay for the output signal to reach the second voltage level V2 and the current leakage. FIG. 2 is the waveforms of the traditional level shifter circuits to show the time delay for the output signal to reach the second voltage level V2. After the input signal is switched from the logic high of the first voltage V1 to the logic low of the ground voltage, it takes more than 80 ns for the voltage of the output signal to reach the second voltage level V2.
FIGS. 3A and 3B show revised level shifter circuits which comprise one or two additional NMOS transistors to reduce the time delay and the leakage current. A third NMOS transistor N3 can be connected parallel to the second PMOS transistor P2 of either type of the traditional level shifter circuit to assist the pull-up of the voltage at the node B to reach the second voltage level V2. In addition, a fourth NMOS transistor N4 can be connected parallel to the first PMOS transistor P1 of either type of the traditional level shifter circuit to assist the pull-up of the voltage at the node A to reach the second voltage level V2.
As shown in FIG. 3A, the third NMOS transistor N3 in response to a control signal at the first voltage level V1 is added. The drain of the third NMOS transistor N3 is connected to the source of the second PMOS transistor P2. The source of the third NMOS transistor N3 is connected to the drain of the second PMOS transistor P2. The gate of the third NMOS transistor N3 is connected to receive the input signal of the first voltage level V1 through an inverter I2. When the input signal is switched from the logic high of the first voltage level V1 to the logic low of the third voltage level Vss, the third NMOS transistor N3, upon receiving the first voltage V1 through its gate, is turned on to assist the pull-up of the voltage at the node B to reach the voltage level V2 faster than the traditional level shifter circuit.
As shown in FIG. 3B, the third NMOS transistor N3 and the fourth NMOS transistors in response to control signals at the first voltage level V1 are added. The third NMOS transistor N3 is connected and operated in the same way as described above. The drain of the fourth NMOS transistor N4 is connected to the source of the first PMOS transistor P1. The source of the fourth NMOS transistor N4 is connected to the drain of the first PMOS transistor P1. The gate of the fourth NMOS transistor N4 is connected to receive the input signal of the first voltage level V1. When the input signal is switched from the logic low of the third voltage level Vss to the logic high of the first voltage level V1, the fourth NMOS transistor N4, upon receiving the first voltage V1 through its gate, is turned on to assist the pull-up of the voltage at the node A to reach the second voltage level V2 faster than the traditional level shifter circuit.
FIG. 4 is the waveforms of the revised level shifter circuits to show the time delay for the output signal to reach the voltage level V2. After the input signal is switched from the logic high of the first voltage V1 to the logic low of the ground voltage, it takes more than 20 ns for the voltage of the output signal to reach the second voltage V2.
The U.S. Pat. No. 7,145,363 describes a level shifter circuit similar to the revised level shifter circuits shown in FIGS. 3A and 3B. However, both the traditional and revised level shifter circuits are not satisfactory in resolving the problems of time delay and current leakage. For traditional level shifter circuits, because the second voltage V2 is high, the threshold voltage of the second PMOS transistor P2 has to be high enough to avoid the damage. As a result, the driving force of the second PMOS transistor P2 is weak and the time delay is very long. For revised level shifter circuits, because the voltage of the control signal for the third NMOS transistor is not high enough, its effect to reduce time delay is very limited. The industry desires level shifter circuits which can further reduce time delay and current leakage.